ncts

In addition to multi-CPU clusters, GPU and DSP, FPGA (field-programmable gate array) is another hardware accelerating approach. High-level synthesis tools from C to FPGA can optimize the implementation under the performance, power, and cost constraints, and enable energy-efficient accelerator-rich architecture. In previous work, we used FPGA for the simultaneous image reconstruction and segmentation with Mumford-shah regularization for XCT under Γ-convergence, and achieved 31X speed-up and 622X energy efficiency compared to CPU implementation. However, FGPA was only used to accelerate the computation of forward and backward projections. Because of the limited memory on chip, recently, we propose asynchronous parallel Kaczmarz (ART) and RAMLA methods with diminishing relaxations. Preliminary results demonstrate better early reconstruction images with both methods. This asynchronous parallel approach fits well with the architecture of FPGA and reduces the communication cost, and is applicable to other parallel architectures in general (e.g. multi-core CPUs). In this talk, we also discuss more general asynchronous parallel data-block and image-block iterative methods with regularization,and approaches to establish their convergence from theoretical perspective. This is a joint work with Jason Cong, Yijin Guan, Peng Li, Guojie Luo, Peter Maass, Thomas Page, Li Shen, Pei Wang, Peng Zhang, Wentai Zhang.